High-performance crystal buffer with ultra-low noise floor of -170 dBc/Hz
Low-power clock fanout buffer with additive jitter of 30 fs RMS (typical, 12k to 20M)
Level translation from 3.3V or 2.5V core supply to output supply of 3.3V, 2.5V, 1.8V or 1.5V
Device consists of primary, secondary and crystal inputs which are selectable through input pins.
Clock inputs can accept LVPECL, LVDS, HCSL, SSTL, LVCMOS or LVTTL signals.
Both differential and single-ended inputs are supported with frequencies from DC to 200MHz.
Support either DC or AC-coupled input interface.