NCS25D31

产品详情

High-performance clock buffer with ultra-low noise floor of -167 dBc/Hz

• Level translation from 3.3V core supply to output supply of 3.3V or 2.5V

• 3：1 input clock multiplexer which is selectable through input pins.

Two universal inputs operate up to 3.1GHz and can accept LVPECL, LVDS, CML, SSTL, HSTL, or HCSL signals

Both differential and single-ended input are supported

Support either DC or AC-coupled input interface

Crystal input frequencies from 8MHz to 50MHz

Crystal overdrive mode with input frequency up to 250MHz
• 10 differential output with Two independent output supply banks

Support LVPECL, LVDS, HCSL or Hi-Z output mode which is selectable per Bank

Ultra-low additive jitter (at 156.25MHz)

43 fs RMS (10K to 20MHz, LVPECL)

52 fs RMS (10K to 20MHz, LVDS)

• Highs PSRR (at 156.25 MHz)-67 dBc LVPECL, -79 dBc LVDS

• LVCMOS reference clock output with independent VCCOC supply and synchronous enable input

Core Supply Voltage(V)：3.3V

Output Supply Voltage(V)：2.5V, 3.3V

Output frequency(Min)(MHz)：-

Output frequency(Max)(MHz)：3100

Additive Jitter(fs)：43

Temperature Range：-40 to 85

Package：49-pin QFN(7mm x 7mm)